1. Field of the Invention
Embodiments of the invention relate generally to a method and system for testing semiconductor chips on a wafer. More particularly, embodiments of the invention relate to a test method and system identifying a localized failure of semiconductor chips on a wafer.
2. Description of the Related Art
The functional heart of all semiconductor devices is an integrated circuit formed on a die of semiconductor compatible material. This die is commonly referred to as a semiconductor “chip.” Semiconductor chips are commercially fabricated in great numbers on material wafers. Wafers are most typically formed from a polished slice of silicon material, but other materials may be used.
The business of fabricating semiconductor chips is a highly competitive one, and fabrication yield (i.e., the percentage of semiconductor chips that actually work out of a total batch of semiconductor chips fabricated on a wafer) is an important business consideration. A couple of yield percentage points up or down is often the difference between profitability and failure. Thus, every aspect of the design, fabrication, and testing of semiconductor chips is ultimately focused on increasing fabrication yield.
Increasing the yield of ever more complicated semiconductor chips is not easy. Contemporary semiconductor chips are fabricated on a wafer using a very complex sequence of different processes. This complex sequence includes a great variety of individual processes ranging across such diverse techniques as photolithography, etching, diffusion, ion implantation, material(s) deposition, etc. Many of these processes form remarkably small elements and regions on the wafer. These elements and regions have extremely narrow fabrication tolerances. Indeed, as integration densities for contemporary semiconductor chips have increased over the past several decades, the respective margins associated with constituent fabrication processes have become increasingly restrictive.
Given the great complexity and the corresponding possibilities for fabrication errors, it is not surprising that semiconductor chips are carefully tested at various stages during their fabrication. Many of these tests are performed on large groups of semiconductor chips as-fabricated on a wafer (i.e., before the individual semiconductor chips are cut from the wafer). This type of testing is generally referred to as “wafer level” testing.
Additional testing takes place once the individual semiconductor chips have been cut from the wafer and packaged to form finished semiconductor devices. Semiconductor device packaging and the corresponding “package level” testing is often conducted by specialized, third-party companies. That is, a semiconductor chip manufacturer may not be involved in the packaging and related package level testing of semiconductor chips. Ideally, every semiconductor chip sent to a packaging vendor by the manufacturer would be a “known good” chip. Accordingly, wafer level testing is an important part of the fabrication sequence ultimately producing a finished semiconductor device.
In addition to understanding which semiconductor chips are “known good”, the manufacturer must also understand yield metrics and trends for wafers passing through the fabrication process. It is quite common for first generation semiconductor chips to have no more than a 70 to 80% yield. Through careful testing, analysis, and fabrication process fine-tuning a manufacturer may increase yield to higher than 99%.
One important metric or analytical tool used by manufacturers in the quest for improved yield is the so-called “wafer map”. A wafer map identifies good chips (GC) from failed chips (FC) in relation to one or more electrical tests performed on the semiconductor chips. More particularly, a wafer map identifies good chips from bad chips in the context of their fabrication arrangement (i.e., spatial proximity one to another) on a wafer. FIGS. 5, 11 and 12 are exemplary wafer maps discussed later in this disclosure.
Manufacturing efficiencies militate towards a system in which a plurality of wafers (typically 25 wafers) are processed in a batch or “lot.” Wafer level testing is conventionally performed on a lot by lot basis to detect and evaluate fabrication process variation(s) resulting in increased or decreased yield. Where an individual wafer within a lot is determined to be defective (e.g., it exhibits an unacceptably low yield), it may be removed from the fabrication process and subjected to a detailed failure analysis. This detailed failure analysis is an expensive and time-consuming process, but it is also a principal step towards improving yield. Accordingly, manufacturers seek to apply their limited quality control resources to the task of failure analysis in the most efficient manner possible in order to obtain the most informative failure analysis.
Thus, the question of defining failure criteria for wafers in a fabrication lot becomes a very important consideration. Further, the ability of manufacturers to coherently capture and appreciate the information resulting from wafer level testing, and wafer failure analysis is critical to their efforts to improve yield. Historically, a threshold or “target yield” has been established for each wafer in a fabrication lot. Those wafers exhibiting an actual yield below the target yield are deemed defective and sent to failure analysis. Those wafers exhibiting yields at or above the target yield are deemed acceptable and are sent out for packaging.
Such a simplistic approach to separating defective and acceptable wafers has proved increasingly unsatisfactory. Further, conventional wafer level testing practices do not provide information on any basis other than a lot by lot basis. Again, this information granularity level is also proving to be increasingly unsatisfactory.